1. Field of the Invention
The present invention relates to solid-state imaging devices. The present invention relates especially to solid-state imaging devices with improved gate electrode portions and to methods for manufacturing the same.
2. Background of the Invention
Various conventional solid-state imaging devices have been proposed (JP H9-283733A, for example). A conventional solid-state imaging device is explained with reference to FIG. 6. An n-type impurity diffusion region 3, a vertical register 4, and a p-type channel stopper region 5 are formed on an n-type silicon substrate 1 inside a first p-type well region 2. A p-type positive charge accumulation region 6 is formed on the n-type impurity diffusion region 3. A second p-type well region 7 is formed directly below the vertical register 4.
Here, a light-receiving portion (photoelectric conversion portion) 8 is configured by a photodiode that is made of a PN junction of the n-type impurity diffusion region 3 and the first p-type well region 2. The light-receiving portion 8 is formed in correspondence to a pixel.
Next, a gate insulating film 9 is formed on the entire surface, including the channel stopper region 5, the vertical register 4, and the positive charge accumulation region 6 of the first p-type well region 2. Furthermore, a first transfer gate electrode 10 and a second transfer gate electrode 11, made with doped amorphous silicon, and a silicon oxide film 12, are formed on the gate insulating film 9 above the first p-type well region 2. A metal light-blocking film 13 is then selectively formed on the first transfer gate electrode 10, the second transfer gate electrode 11, and the silicon oxide film 12.
The first transfer gate electrode 10 and the second transfer gate electrode 11 of the above structure are manufactured by the following process shown in FIGS. 7A–D. After forming the gate insulating film 9 on the entire surface of the n-type silicon substrate 1 by utilizing an oxidation furnace and a LPCVD reactor, a first n-type doped amorphous silicon film 14 with a thickness of about 0.5 μm is formed on the entire surface of the gate insulating film 9 in one layer at a uniform concentration (approximately 7.0×1020 cm−3) inside the LPCVD reactor by utilizing the thermal decomposition shown in the chemical reaction (1) below (FIG. 7A).PH3+SiH4→Si(phosphorus diffusion)+2H2  (1)
Next, the first transfer gate electrodes 10 are formed by photolithography and etching, leaving a gate region and a gate wiring region of the first doped amorphous silicon film 14 as is.
The first transfer gate electrodes 10 are then oxidized with the oxidation furnace to form the silicon oxide film 12 (FIG. 7B). A second n-type doped amorphous silicon film 15 with a thickness of about 0.5 μm is formed on the entire surface in one layer at a uniform concentration (approximately 7.0×1020 cm−3) inside the LPCVD reactor by utilizing the thermal decomposition shown in the chemical reaction below (FIG. 7C).PH3+SiH4→Si(phosphorus diffusion)+2H2  (2)
Next, the second transfer gate electrodes 11 are formed by photolithography and etching, leaving a gate region and a gate wiring region of the second doped amorphous silicon film 15 as is. The second transfer gate electrodes 11 are then oxidized with the oxidation furnace to form the silicon oxide film 12 (FIG. 7D).
However, the method for manufacturing the conventional solid-state imaging device has the following problems.
The first problem is the formation of local microcrystal regions 16 in the n-type impurity doped amorphous silicon layer when forming the first doped amorphous silicon film 14 or the second doped amorphous silicon film 15 on the entire surface in one layer with the n-type impurity doped amorphous silicon layer of a thickness of about 0.5 μm at a uniform concentration (approximately 7.0×1020 cm−3) by utilizing the thermal decomposition: PH3+SiH4→Si (phosphorus diffusion)+2H2 inside the LPCVD reactor (FIG. 8A).
The etching rate of the microcrystal regions 16 is faster than that of other regions when the n-type impurity doped amorphous silicon layers that are formed on the entire surface are etched in the next step.
Therefore, though the probability is statistically low, the microcrystal regions 16 may form in the places where the microcrystal regions 16 are in contact with the gate insulating film 9 that is formed below when the n-type impurity doped amorphous silicon layers that are formed on the entire surface are etched. In this case, since the etching rate of these microcrystal regions 16 is faster than that of other regions, the gate insulating film 9 that is formed below is locally over-etched and locally thin regions 17 result on the gate insulating film 9 that is formed below (see FIG. 8B).
If the locally thin regions 17 of the gate insulating film 9 are formed at transfer register regions for charge transfer, then local potential barriers 18 develop in the transfer channel, the charge is trapped and the charge transfer may become incomplete (see FIG. 8C).
The second problem is the phenomenon of imaging defects that occurs at an average n-type impurity concentration of the n-type impurity doped amorphous silicon layer of 7.0×1020 cm−3, for example (FIG. 9A). The phenomenon occurs when the first doped amorphous silicon film 14 or the second doped amorphous silicon film 15 is formed on the entire surface in one layer with the n-type impurity doped amorphous silicon layer of a thickness of about 0.5 μm at a uniform concentration by utilizing the thermal decomposition: PH3+SiH4→Si (phosphorus diffusion)+2H2 inside the LPCVD reactor (FIG. 9A). Numeral 16 in FIG. 9A denotes a microcrystal region.
The phenomenon can be explained with the following model. If the n-type impurity doped amorphous silicon layer is subjected to the thermal diffusion in the next step, then silicon grains 19 in the n-type impurity doped amorphous silicon layer grow and a high concentration of n-type impurities 21 occurs in the vicinity of silicon boundaries 20 of the grown silicon grains 19 (FIG. 9B).
As a result, there is a localized increase in the resistance of the n-type impurity doped amorphous silicon layer and an image defect akin to a broken conductor may occur by inhibition of the flow of electrons in the doped amorphous silicon layer or by the electrons remaining in the doped amorphous silicon layer.
As for the third problem, the second transfer gate electrode 11 of the conventional solid-state imaging device has the function of reading the charge from the light-receiving portion to the vertical register and another function of charge transfer within the vertical register, as illustrated in FIG. 6. Therefore, a maximum pulse voltage of about 25V is applied to the insulating film that insulates the first transfer gate electrode 10 and the second transfer gate electrode 11.
And although the insulating film (the silicon oxide film 12) is formed by thermal oxidation of the first transfer gate electrode 10, as explained in FIG. 7, the withstand voltage of the film obtained by subjecting the n-type impurity doped amorphous silicon to the thermal oxidation is generally weak and a field strength of about 1 to 2 Mv/cm is obtained. Therefore, in order to obtain a withstand voltage of 25 V, the thickness of the oxide film above the n-type impurity doped amorphous silicon needs to be in the order of at least 0.3 μm.
There is a need for the improvement in particular of conventional solid-state imaging devices with large surface area, in which withstand voltage defects of the oxide film greatly lower the yield. In FIG. 6, if the thickness of the oxide film is thick, then the level difference between the portion in which the first transfer gate electrode 10 and the second transfer gate electrode 11 are stacked and the light-receiving portion in which these electrodes are not formed becomes 1 μm.
Therefore, the metal light-blocking film 13 for blocking light that is provided on top of the electrodes may not cover the level difference well and the coverage may be thin in the level difference portion. If there is such a thin portion, then a false signal may arise and the S/N ratio may deteriorate because light may leak into the vertical register and the charge generated from photoelectric conversion in the vertical register 4 is added to the signal charge.
Furthermore, if the metal light-blocking film 13 for blocking light is used as a conductor, then the problem may occur that no voltage is applied because the conductor is cut at the level difference portion. From the above, there is a need for the formation of an insulating film that is thin and has withstand properties.